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| 1/16 www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. high reliability series serial eeprom series wl-csp eeproms family spi bus br25s128guz-w description br25s128guz-w is a 16k 8bit serial eeprom of spi bus interface method. features 1) high speed clock action up to 10mhz (max.) 2) wait function by holdb terminal 3) part or whole of memory arrays settable as read only memory area by program 4) 1.7 5.5v single power source action most suitable for battery use 5) 64byte page write mode useful for in itial value write at factory shipment 6) for spi bus interface (cpol, cpha)=(0, 0), (1, 1) 7) auto erase and auto end function at data rewrite 8) low current consumption at write action (5.0v) : 1.5ma (typ.) at read action (5.0v) : 1.0ma (typ.) at standby action (5.0v) : 0.1 a (typ.) 9) address auto increment function at read action 10) write mistake prevention function write prohibition at power on write prohibition by command code (wrdi) write prohibition by wpb pin write prohibition block setting by status registers (bp1, bp0) write mistake prevention function at low voltage 11) vcsp35l2 package 12) data at shipment memory array: ffh, status register wpen, bp1, bp0 : 0 13) data kept for 40 years 14) data rewrite up to 1,000,000 times no.11001jbt06
technical note 2/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. absolute maximum ratings (ta=25 ) parameter symbol limits unit impressed voltage vcc -0.3 +6.5 v permissible dissipation pd vcsp35l2 220 1 mw storage temperature range ts t g - 6 5 +125 operating temperature range topr -40 +85 terminal voltage -0.3 vcc+0.3 2 v 1 degradation is done at 4.5mw, for operation above 25 . 2 the max value of terminal voltage is not over 6.5v. memory cell characteristics (ta=25 , vcc=1.7v 5.5v) parameter limits unit min. typ. max. number of data rewrite times 1 1,000,000 time data hold years 1 40 year 1 not 100% tested. recommended action conditions parameter symbol limits unit power source voltage vcc 1.7 5.5 v input voltage v in 0 vcc input / output capacity (ta=25 , frequency=5mhz) parameter symbol cond itions min. max. unit input capacity 1 c in v in =gnd 8 pf output capacity 1 c out v out =gnd 8 1 not 100% tested. electrical characteristics (unless otherwise specified, ta=-40 +85 , vcc=1.7 5.5v) parameter symb ol limits unit conditions min. typ. max. ?h? input voltage1 vih1 0.7xvcc vcc+0.3 v 1.7 Q vcc Q 5.5v ?l? input voltage1 vil1 -0.3 0.3xvcc v 1.7 Q vcc Q 5.5v ?l? output voltage1 vol1 0 0.4 v iol=2.1ma, 2.5 Q vcc<5.5v ?l? output voltage2 vol2 0 0.2 v iol=1.0ma, 1.7 Q vcc<2.5v ?h? output voltage1 voh1 vcc-0.2 vcc v ioh=-0.4ma, 2.5v Q vcc<5.5v ?h? output voltage2 voh2 vcc-0.2 vcc v ioh=-100 a, 1.7 Q vcc<2.5v input leakage current ili -1 1 a v in =0 vcc output leakage current ilo -1 1 a v out =0 vcc, csb=vcc operating current write icc1 0.5 ma vcc=1.8v,fsck=5mhz, te/w=5ms byte write page write icc2 1 ma vcc=2.5v,fsck=10mhz, te/w=5ms byte write page write icc3 2 ma vcc=5.5v,fsck=10mhz, te/w=5ms byte write page write operating current read icc4 1 ma vcc=1.8v,fsck=5mhz, so=open read, read status register icc5 1 ma vcc=2.5v,fsck=2mhz, so=open read, read status register icc6 1.5 ma vcc=2.5v,fsck=5mhz, so=open read, read status register icc7 2 ma vcc=2.5v,fsck=10mhz, so=open read, read status register icc8 2 ma vcc=5.5v,fsck=5mhz, so=open read, read status register icc9 4 ma vcc=5.5v,fsck=10mhz, so=open read, read status register icc10 8 ma vcc=5.5v,fsck=20mhz, so=open read, read status register standby current isb 2 a vcc=5.5v, csb=vcc, sck=si=vcc or gnd holdb=wpb=vcc, so=open radiation resistance design is not made technical note 3/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. block diagram operating timing characteristics (ta=-40 +85 , unless otherwise specified, load capacity c l =30pf) parameter symbol 1.7 Q vcc<2.5v 1.8 Q vcc<2.5v 2.5 Q vcc Q 5.5v unit min. typ. max. min. typ. max. min. typ. max. sck frequency f sck - - 3 - - 5 - - 10 mhz sck high time t sckwh 125 - - 80 - - 40 - - ns sck low time t sckwl 125 - - 80 - - 40 - - ns csb high time t cs 250 - - 90 - - 40 - - ns csb setup time t css 100 - - 60 - - 30 - - ns csb hold time t csh 100 - - 60 - - 30 - - ns sck setup time t scks 100 - - 50 - - 20 - - ns sck hold time t sckh 100 - - 50 - - 20 - - ns si setup time t dis 30 - - 20 - - 10 - - ns si hold time t dih 50 - - 20 - - 10 - - ns data output delay time t pd - - 125 - - 80 - - 40 ns output hold time t oh 0 - - 0 - - 0 - - ns output disable time t oz - - 200 - - 80 - - 40 ns holdb setting setup time t hfs 100 - - 0 - - 0 - - ns holdb setting hold time t hfh 100 - - 20 - - 10 - - ns holdb release setup time t hrs 100 - - 0 - - 0 - - ns holdb release hold time t hrh 100 - - 20 - - 10 - - ns time from holdb to output high-z t hoz - - 100 - - 80 - - 40 ns time from holdb to output change t hpd - - 100 - - 80 - - 40 ns sck rise time 1 t rc - - 1 - - 1 - - 1 s sck fall time 1 t fc - - 1 - - 1 - - 1 s output rise time 1 t ro - - 100 - - 50 - - 40 ns output fall time 1 t fo - - 100 - - 50 - - 40 ns write time t e/w - - 5 - - 5 - - 5 ms 1 not 100% tested fig.1 block diagram instruction decode control clock generation voltage detection write inhibition high voltage generator instruction register 131,072 bit eeprom 8bit 14bit address register data register address decoder r/w amp 14bit csb sc k si holdb wpb so 8bit technical note 4/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. pin assignment and description sync data input / output timing ac measurement conditions parameter symbol limits unit min. typ. max. load capacity c l - - 30 pf input rise time - - - 50 ns input fall time - - - 50 ns input voltage - 0.2vcc/0.8vcc v input / output judgment vo ltage - 0.3vcc/0.7vcc v terminal name input/output function csb input chip select input so output serial data output wpb input write protect input write command is prohibited write status register command is prohibited gnd - all input / output reference voltage, 0v si input start bit, ope code, address, and serial data input sck input serial clock input holdb input hold input command communications may be suspended temporarily (hold status) vcc - power source to be connected fig.3 input timing csb sck si so tcs tcss tscks tsckwl tsckwh tdis tdih trc tfc high-z si is taken into ic inside in sync with data rise edge of sck. input address and data from the most significant bit msb fig.4 input / output timing csb sck si so tpd toh tro,tfo toz tcsh tsckh tcs hi g h-z fig.5 hold timing csb sck si n+1 "h" "l" n dn n-1 dn dn-1 holdb so dn+1 thfs thfh thoz thrs thrh tdis thpd high-z so is output in sync with data fall edge of sck. data is output from the most significant bit msb. a1 nc a2 a3 sck nc b1 b2 b3 c3 c2 c1 d1 d2 d3 nc nc si gnd holdb so wpb vcc csb a b c d 1 2 3 fig.2 pin assignment diagram (bottom view) technical note 5/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following characteristic data are typ. values.) 0 0.2 0.4 0.6 0.8 1 0123456 iol[ma] vol1[v] ta=-40 ta=25 ta=85 spec fig.8 "l" output voltage vol1 (vcc=2.5v) 2.2 2.3 2.4 2.5 2.6 0 0.4 0.8 1.2 ioh[ma] voh1[v] ta=-40 ta=25 ta=85 spec fig.9 "h" output voltage voh1 (vcc=2.5v) -0.5 0 0.5 1 1.5 0123456 vcc[v] ili[a] ta=-40 ta=25 ta=85 spec fig.10 input leak current ili(csb,sck,si,holdb,wpb) -0.5 0 0.5 1 1.5 0123456 vout[v] ilo[a] spec ta=-40 ta=25 ta=85 fig.11 output leak current ilo(so) 0 2 4 6 8 10 0123456 vcc[v] icc10[ma] data=00h ta=-40 ta=25 ta=85 spec fig.13 current consumption at read operation icc10 -1 0 1 2 3 4 5 0123456 vcc[v] isb[a] spec ta=-40 ta=25 ta=85 fig.14 current consumption at standby operation i s 1 10 100 1000 0123456 vcc[v] fsck[mhz] ta=-40 ta=25 ta=85 spec spec spec fig.15 sck frequency fsck 0 20 40 60 80 100 120 140 0123456 vcc[v] tsckwh [ns] spec ta=-40 ta=25 ta=85 spec spec fig.16 sck high time tsckwh 0 20 40 60 80 100 120 140 0123456 vcc[v] tsckwl [ns] spec ta=-40 ta=25 ta=85 spec spec fig.17 sck low time tsckwl 0 50 100 150 200 250 300 0123456 vcc[v] tcs[ns] ta=-40 ta=25 ta=85 spec spec spec fig.18 csb high time tcs 0 20 40 60 80 100 120 0123456 vcc[v] tcss[ns] ta=-40 ta=25 ta=85 spec spec spec fig.19 csb setup time tcss 0 20 40 60 80 100 120 0123456 vcc[v] tcsh[ns] spec ta=-40 ta=25 ta=85 spec spec fig.20 csb hold time tcsh 0 1 2 3 4 5 6 0123456 vcc[v] vih[v] spec ta=-40 ta=25 ta=85 fig.6 "h" input voltage vih(csb,sck,si,holdb,wpb) 0 1 2 3 4 5 6 0123456 vcc[v] vil[v] spec ta=-40 ta=25 ta=85 fig.7 "l" input voltage vil(csb,sck,si,holdb,wpb) 0 1 2 3 4 0123456 vcc[v] icc3[ma] data=00h ta=-40 ta=25 ta=85 spec fig.12 current consumption at write operation icc3 technical note 6/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following characteristic data are typ. values.) fig.29 output rise time tro 0 20 40 60 80 100 120 0123456 vcc[v] tro [ns] ta=-40 ta=25 ta=85 spec spec spec -10 0 10 20 30 40 50 60 0123456 vcc[v] tdih[ns] ta=-40 ta=25 ta=85 spec spec spec fig.22 si hold time tdih 0 30 60 90 120 150 180 210 0123456 vcc[v] toz [ns] ta=-40 ta=25 ta=85 spec spec spec fig.24 output disable time toz 0 20 40 60 80 100 120 0123456 vcc[v] thfh [ns] ta=-40 ta=25 ta=85 spec spec spec fig.25 holdb setting hold time thfh -10 10 30 50 70 90 110 130 0123456 vcc[v] thrh [ns] ta=-40 ta=25 ta=85 spec spec spec fig.26 holdb release hold time thrh 0 20 40 60 80 100 120 0123456 vcc[v] thoz [ns] ta=-40 ta=25 ta=85 spec spec spec fig.27 time from holdb to output high-z thoz 0 20 40 60 80 100 120 0123456 vcc[v] thpd [ns] ta=-40 ta=25 ta=85 spec spec spec fig.28 time from holdb to output change thpd 0 20 40 60 80 100 120 0123456 vcc[v] tfo [ns] spec spec spec ta=- 40 ta=25 fig.30 output fall time tfo fig.21 si setup time tdis 0 10 20 30 40 50 0123456 vcc[v] tdis[ns] ta=-40 ta=25 ta=85 spec spec spec 0 20 40 60 80 100 120 140 0123456 vcc[v] tpd [ns] spec ta=-40 ta=25 ta=85 spec spec fig.23 data output delay time pd 0 2 4 6 8 0123456 vcc[v] te/w[ms] spec ta=-40 ta=25 ta=85 fig.31 write cycle time te/w technical note 7/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. features status registers this ic has status register. the status register expresses the following parameters of 8 bits. bp0 and bp1 can be set by write status register command. t hese 2 bits are memorized into the eeprom, therefore are valid even when power source is turned off. rewrite characteristics and data hold time ar e same as characteristics of the eeprom. wen can be set by write enable command and write disable command. wen becomes write disable status when power source is turned off. r/b is for write conf irmation, therefore cannot be set externally. the value of status register can be read by read status register command. 1. contexture of status register product number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 br25s128guz-w wpen 0 0 0 bp1 bp0 wen r/b bit memory location function wpen eeprom wpb pin enable / disable designation bit wpen=0=invalid wpen=1=valid bp1 bp0 eeprom eeprom write disable block designation bit wen registers write and write status register write enable / disable status confirmation bit wen=0=prohibited wen=1=permitted r/b registers write cycle status (ready / busy) status confirmation bit r/b=0=ready r/b=1=busy 2. write disable block setting bp1 bp0 write disable block br25s128guz-w 0 0 none 0 1 3000h-3fffh 1 0 2000h-3fffh 1 1 0000h-3fffh wpb pin by setting wpb=low, write command is prohibited. and t he write command to be disabled at this moment is wrsr. however, when write cycle is in execution, no interruption can be made. product number wrsr write br25s128guz-w prohibition possible but wpen bit ?1? prohibition impossible holdb pin by holdb pin, data transfer can be interrupted. when sck=?0?, by making holdb from ?1 ? into?0?, data transfer to eeprom is interrupted. when sck = ?0?, by making holdb from ?0? into ?1?, data transfer is restarted. technical note 8/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. command mode command contents ope code wren write enable command 0000 0110 wrdi write disable command 0000 0100 read read command 0000 0011 write write command 0000 0010 rdsr read status register command 0000 0101 wrsr write status register command 0000 0001 timing chart 1. write enable (wren) / disable (wrdi) command this ic has write enable status and write disable status. it is set to write enable status by write enable command, and it is set to write disable status by write disable comm and. as for these commands, set csb low, and then input the respective ope codes. the respective co mmands are accepted at the 7-th clock rise. even with input over 7 clocks, command becomes valid. when to carry out write command, it is necessary to set writ e enable status by the write enable command. if write command is input in the write disable status, the command is cancelled. and even in the write enable status, once write command is executed, it gets in the write disable status. afte r power on, this ic is in write disable status. 2. read command (read) by read command, data of eeprom can be read. as for this command, set csb low, then input address after read ope code. eeprom starts data output of the designated addr ess. data output is started from sck fall of 23-th clock, and from d7 to d0 sequentially. this ic has increment read function. after output of data for 1 byte (8bits), by continuing input of sck , data of the next address can be read. in crement read can read all the addresses of eeprom. after reading data of the most significant address, by continuing increment r ead, data of the most insignificant address is read. wren (write enable): write enable fig.32 write enable command high-z 6 03 7 12 45 csb sck so si 00000110 fig.33 write disable command wrdi (write disable): write disable high-z 0000 si 0100 03 12 4 7 csb sck 5 6 so high-z 11 1 1 0 0 3 7 1 2 d6 so csb sck si 4 5 a12 6 8 * a0 a1 d7 23 30 24 d0 0 0 0 0 0 d2 d1 9 10 a13 30 31 * fig.34 read command technical note 9/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. 3. write command (write) by write command, data of eeprom can be written. as for th is command, set csb low, then input address and data after write ope code. then, by making csb high, the eeprom starts writing. the write time of eeprom requires time of te/w (max 5ms). during te/w, other than read status register comm and is not accepted. set csb high between taking the last data (d0) and rising the next sck clock. at the other timing , write command is not executed, and this write command is cancelled. this ic has page write function, and after input of data for 1 byte (8 bits), by continuing data input without setti ng csb high, 2byte or more data can be written for one te/w. up to 64 arbitrary bytes can be written. in page write, the insignificant 6 bit of the designated address is incremented internally at every ti me when data of 1 byte is input and data is written to respective addresses. when data of the maximum bytes or higher is input, address rolls over, and previously input data is overwritten. 4. read status register command (rdsr) write status register command can write dat a of status register. the data can be wri tten by this command are 3 bits, that is, wpen(bit7), bp1 (bit3) and bp0 (bit2) am ong 8 bits of status register. by bp1 and bp0, write disable block of eeprom can be set. as for this command, set csb low, and input ope code of write status regist er, and input data. then, by making csb high, eeprom starts writing. wr ite time requires time of te/w as sa me as write. as for csb rise, set csb high between taking the last data bit (bit0) and the next sck clock rising. at the other timing, command is cancelled. write disable block is determined by bp1 bp0, and the block can be sele cted from 1/4 , 1/2, and entire of memory array (refer to the write disable block setting table.). to the write disa bled block, write cannot be made, and only read can be made. high-z 9? =don't care 31 d0 0 0 0 0 0 d2 d1 d7 23 30 24 d6 0 a0 a1 * 1 1 2 4 0 csb sck si so 0 3 7 8 5 6 a12 11 9 10 a13 * fig.35 write command csb sck high-z *=don't care 0 0 0 0 1 wpen 0 1 2 4 0 si so 0 3 7 8 5 6 * 9 10 11 12 13 14 15 * * bp1 bp0 * * bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 fig.36 write status register fig.37 read status register command high-z bit7 bit6 bit5 bit4 0 0 0 bit3 bit2 bit1 bit0 13 csb sck si 1 1 10 6 0 so 14 1 2 wen r/b 11 15 3 7 9 0 5 12 0 0 0 0 0 4 8 wpen bp1 bp0 technical note 10/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. wpb cancel valid area wpb is normally fixed to ?h? or ?l? for use, but when wpb is c ontrolled so as to cancel write status register command, pay attention to the follo wing wpb valid timing. while write status register command is executed, by setting w pb = ?l? in cancel valid area, command can be cancelled. the area from command ope code to csb rise at internal auto matic write start becomes the cancel valid area. however, once write is started, by any input write cycle cannot be cancelled. wpb input becomes don?t care, and cancellation becomes invalid. holdb pin by holdb pin, command communication can be stopped tempor arily (hold status). the command communications are carried out when the holdb pin is high. to get in hold status, at command communication, when sck=low, set the holdb pin low. at hold status, sck and si become don?t care, and so becomes high impedance (high-z). to release the hold status, set the holdb pin high when sck=low. af ter that, communication can be restarted from the point before the hold status. for example, when hold status is made after a5 address input at read, after release of hold status, by starting a4 address input, read can be restar ted. when in hold status, k eep csb low. when it is set csb=high in hold status, the ic is reset, theref ore communication after that cannot be restarted. fig.38 wpb valid timing (at inputting wrsr command) 6 7 ope code data te/w data write time sck 15 16 valid (wrsr command is reset by wpb=l) invalid technical note 11/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. method to cancel each command read, rdsr ? method to cancel : cancel by csb = ?h?. write page write a ope code or address input area cancellation is available by csb=?h?. b data input area (d7 d1 input area) cancellation is available by csb=?h?. c data input area (d0 area) in this area, cancellation is not available. when csb is set high, write starts. by continuing to input sck clock without rising csb, the command will be page write command. in page write mode, there is write enable area at every 8 clocks. d te/w area in the area c, by rising csb, write starts. while writting, by any input, cancellation cannot be made. note1) if vcc is made off during write ex ecution, designated address data is not guar anteed, therefore write it once again. note2) if csb is rised at the same timing as that of the sck rise, write execution / c ancel becomes unstable, therefore, it is recommended to rise in sck = ?l? area. as for sck rise, assure timing of tc ss / tcsh or more. wrsr a from ope code to 15-th clock rise cancellation is available by csb=?h?. b from 15-th clock rise to 16-th clock rise (write enable area) this area, cancellation is not available when csb is set high, write starts. c after 16-th clock rise. cancellation is available by csb=?h?. however, if write starts (csb is rised) in the area b, cancellation cannot be made by any means. and, by inputting on sck clock, cancellation cannot be made. note1) if vcc is made off during write ex ecution, designated address data is not guar anteed, therefore write it once again note2) if csb is rised at the same timing as that of the sck rise, write execution / c ancel becomes unstable, therefore, it is recommended to rise in sck = ?l? area. as for sck rise, assure timing of tc ss / tcsh or more. wren/wrdi a from ope code to 7-th clock rise, cancellation is available by csb = ?h?. b cancellation is not available 7-th clock. fig.39 read cancel valid timing fig.40 rdsr cancel valid timing fig.43 wren/wrdi cancel valid timing ope code address a data te/w b d c 8bits 8bits d7 b d6 d5 d4 d3 d2 d1 d0 sck si c fig.42 wrsr cancel valid timing ope code address cancel available in all areas of read mode data 8 bits 8 bits ope code cancel available in all areas of rdsr mode data 8 bits 8 bits ope code data te/w 8 bits 14 15 16 17 d1 d0 a b c 8 bits a b c sck si ope code 8 bits 6 7 8 a b sck fig.41 write cancel valid timing technical note 12/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. i/o peripheral circuits in order to realize stable high speed operations, pay a ttention to the following input / output pin conditions. input pin pull up, pull down resistance when to attach pull up, pull down resistance to eeprom i nput pin, select an appropriate value for the microcontroller vol, iol with considering vil characteristics of this ic. 1. pull up resistance and, in order to prevent malfunction or erroneous write at power on/off, be sure to make csb pull up. 2.pull down resistance further, by amplitude vihe, vile of signal input to eeprom, operation speed changes. by inputting vcc/gnd level amplitude of signal, more stable high speed operations can be realized. on the contrary , when amplitude of 0.8vcc / 0.2vcc is input, operation speed becomes slow. *1 in order to realize more stable high speed operati on, it is recommended to make the values of r pu , r pd as large as possible, and make the amplitude of signal input to eeprom close to the amplitude of vcc / gnd level. ( 1 in this case, guaranteed value of operating timing is guaranteed.) fig.44 pull up resistance fig.45 pull down resistance r pd R v ohm i ohm ??? v ohm R v ihe ??? example) when v cc =5v, v ohm =v cc -0.5v, i ohm 0.4ma, v ihe =v cc 0.7v, from the equation , r pd R 5 0.5 0.410 -3 r pd R 11.3[k ] r pu R v cc v olm i olm ??? v olm Q v ile ??? r pu R 5 0.4 210 - 3 r pu R 2.3[k ] with the value of rpu to satisfy the above equation, v olm becomes 0.4v or lower, and with v ile (=1.5v), the equation is also satisfied. ? v ile :eeprom v il specifications ? v olm :microcontroller v ol specifications ? i olm :microcontroller i ol specifications example) when vcc=5v, v ile =1.5v, v olm =0.4v, i olm =2ma, from the equation , i olm v ile v olm ?l? output ?l? input microcontroller eeprom r pu i ohm v ihe v ohm microcontroller eeprom ?h? output ?h? input r pd technical note 13/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. so load capacity condition load capacity of so output pin affects upon delay characterist ic of so output (data output delay time, time from holdb to high-z, output rise time, output fall time.). in order to make output delay char acteristic into better, make so load capacity small. other cautions make the each wire length from the microcontroller to eepro m input pin same length, in order to prevent setup / hold violation to eeprom, owing to difference of wire length of each input. equivalent circuit output circuit input circuit eeprom so c l fig.46 so load capacity of data output delay time tpd holdb wpb fig.51 holdb input equivalent circuit fig.52 wpb input equivalent circuit oeint. so fig.47 so output equivalent circuit csb reset int. fig.48 csb input equivalent circuit sck si fig.49 sck input equivalent circuit fig.50 si input equivalent circuit technical note 14/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. notes on power on/off at standby set csb ?h?, and be sure to set sck, si input ?l? or ?h?. do not input intermediate electric potantial. at power on/off when vcc rise or fall, set csb=?h? (=vcc). when csb is ?l?, this ic gets in input ac cept status (active). if power is turned on in this status, noises and the likes may cause malfunction, erroneous write or so . to prevent these, at power on, set c sb ?h?. (when csb is in ?h? status, all inputs are canceled.) (good example) csb terminal is pulled up to vcc. at power off, take 10ms or more before supply. if po wer is turned on without observing this condition, the ic internal circuit may not be reset. (bad example) csb terminal is ?l? at power on/off. in this case, csb always becomes ?l? (active status), and eeprom may have malfunction or erroneous write owing to noises and the likes. even when csb input is high-z, the status becomes like this case. operating timing after power on as shown in fig.55, at standby, when sck is ?h?, even if csb is fa llen, si status is not read at fall edge. si status is read at sck rise edge after fall of csb. at standby and at power on/off, set csb ?h? status. at power on malfunction preventing function this ic has a por (power on reset) circuit as mistake writ e countermeasure. after por acti on, it gets in write disable status. the por circuit is valid only when power is on, and does not work when power is off. when power is on, if the recommended conditions of the following tr, toff, and vbot are not satisfied, it may become write enable status owing to noises and the likes. recommended conditions of t r , t off , vbot t r t off vbot 10ms or below 10ms or higher 0.3v or below 100ms or below 10ms or higher 0.2v or below low voltage malfunction preventing function lvcc (vcc-lockout) circuit prevents data rewrite ac tion at low power, and prevents wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. tr toff vbo t 0 vcc fig.53 csb timing at power on/off csb vcc bad example good example fig.55 rise waveform fig.54 operating timing 0 1 2 command start here. si is read. even if csb is fallen at sck=?h?, si status is not read at that edge. csb sck si technical note 15/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. noise countermeasures vcc noise (bypass capacitor) when noise or surge gets in the power source line, malfunc tion may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1 f) between ic vcc and gnd. at that ti me, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. sck noise when the rise time of sck (trc) is long, and a certain degr ee or more of noise exists, malfunction may occur owing to clock bit displacement. to avoid this, a schmitt trigger circuit is built in sck input. the hysterisis width of this circuit is set about 0.2v, if noises exist at sck input, set the noise amplit ude 0.2vp-p or below. and it is recommended to set the rise time of sck (trc) 100ns or below. in the case when the rise time is 100ns or higher, take sufficient noise countermeasures. make the clock rise, fall time as small as possible. wpb noise during execution of write status regist er command, if there exist noises on w pb pin, mistake in recognition may occur and forcible cancellation may result. to avoid this, a schmitt trigger circuit is built in wpb input. in the same manner, a schmitt trigger circuit is built in c sb input, si input and holdb input too. cautions on use (1) described numeric values and data are design repr esentative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characterist ics and transition characteristics and fluc tuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed vo ltage and operating temperatur e range and so forth are exceeded, lsi may be destructed. do not impress volta ge and temperature exceeding the absolute maximum ratings. in the case of fear exceeding the absolut e maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is higher than that of gnd terminal. (5) heat design in consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. (6) terminal to terminal short circuit and wrong packaging when to package lsi onto a board, pay sufficient attentio n to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of short circuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause malfunction, therefore, ev aluate design sufficiently. technical note 16/16 br25s128guz-w www.rohm.com 2011.11 - rev.b ? 2011 rohm co., ltd. all rights reserved. ordering part number b r 2 5 s 1 2 8 g u z - w e 2 part no. bus type 25:spi operating temperature / power source voltage s: -40 ~ +85 / 1.7v~5.5v capacity 128=128kbit package guz:vcsp35l2 double cell packaging and forming specification e2: embossed tape and reel package specifications (unit : mm) vcsp35l2 (br25s128guz-w) 23 1 a b c d s 0.06 s 2.000.05 0.4max 2.630.05 0.100.05 b a 0.05 0.500.05 12- 0.250.05 p=0.5 2 0.5650.05 p=0.5 3 b a 1pin mark ? order quantity needs to be multiple of the minimum quantity. www.rohm.com ? 2011 rohm co., ltd. all rights reserved. notice ] ?? ???w ??hx ? ???w?dsxz 8l~ ?b?\q?nxs ??`?b{ ???wgl o0x~?srwh?'sx!?b?\quk??b{ ???tgl^?om? o0x a ?w] op??pb{]?;tkh??`oxz m?7 {? ?c ] e{woqz ]? yxi^m{ ???tgl^?os??b ;s???fw :srw ?ctmv?`oxz? a ?w a j $s ?^??mm? ?b??wpb{ `hum?`oz?? ?-?^?? ?txz? ? ~ e??? `omhiv?b?os&mmh`?b{ ? ? ? t g l ^ ? o s ? ? b ? c x z y ? ? 8 b h ? ? o t ^ r ` h ? w p b u za u z p ? ? c w ??~? ti?b? ?usl7t \ah ?tsmo?z ?xfw y ? ?o?wpxk??d?{ ???tgl^?os??bu [ ?cxz a ?w e $ ?^s?| ;s??sr??`h?wpk?z ??hx tw ? $r?vfw wk???vbtmmo? $t??? $t?z fw?a?hx b;?? zb??wpxk??d?{ gu [ ?cw?;ti?`o u c \`h ?z ?x fw y ? ?o?wpxk??d?{ ???t l^?os??b a ?xz ` $s ??;+ " 7;+z 0 ";+z ?;+zh ? a ?z ????y??;+sr?w?;?? $`om?b{ ???t l^?os??b a ?xz ? 1l ?-xs^?os??d?{ ?x t ?~ ?t qw2 t ? ?ps??buz ?wa?p? ?b?\q?k? ??b{ ? a ?u? ?`hmz fw1t?? ??zpb ? sui\?sm?o]?;;+pw ???a???z ? ? ?-z ?w-z ????? sw? ??-?s&m`?b{ ? qh ]?;??; w ?? {u ??omsm ?z mts? y ??x ?o?wpxk??d?{ ??o? ss ?t qua{^?z fw a ?w? ??? ?^u ? ??t`k?mx .t)?? t?bsf?wk?;+~ ?~3a ??;+z ;+z? |;zj?? m?z ? m?z ? ? ?sr?w]?;?? $`o ?-~ a ^?h?wpxk??d?{ g ? ; mt?; ^?h ?z mts? y ??x ?o?wpxk??d?{ g ? ; m?w?;?u |^??m xz ? 2t?? ?p] ?&m?b{ ???tgl^?os??b a ?s?|u [woj ??? 8t|?u?o t? pb? a ??hx u [? zb? ?z ?hx?t ?b? ?txz ?ot,nx?du ?apb{ ? a ?w]u |k?uqo]_m?b{ ?? ?`m?????sr];?`os??bwpz sedxi^m{ rohm customer support system http://www.rohm.co.jp/contact/ r1120 a |
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